Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-84 Freescale Semiconductor
Figure 19-46. RFIFO Diagram
The detailed behavior of the pop next data pointer and receive next data pointer is described in the example
shown in Figure 19-47 where an RFIFO with 16 entries is shown for clarity of explanation, the actual
hardware implementation has only four entries. In this example, RFIFOn with 16 entries is shown in
sequence after popping or receiving entries.
Pop Next
Data Entry 1
Data Entry 2
Control Signals
RFIFO
Counter Control
Logic
Data Pointer *
Receive Next
Data Pointer *
Data from
External
Device or
from
On-Chip
Read
from Bus
Interface
by CPU
or DMA
DMA Done
Interrupt/DMA Request
All RFIFO entries are memory mapped and the entries addressed by these pointers
can have their absolute addresses calculated using POPNXTPTR and RFCTR.
*
RFIFO
Pop Register
ADCs
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