NXP Semiconductors MPC5566 - Page 884

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-81
Figure 19-44. Non-Coherency Event When Different CFIFOs Are Using Different External Command Buffers
eQADC SSI
CFIFO5
CF5_3_CM3
3
CF5_3_CM2
2
Sent
1
Sent
0
TNXTPTR*
Command Buffer 2
Empty
1
Empty
0
CFIFO0 and CFIFO5 both have commands
CFIFO0
CF0_2_CM3
3
CF0_2_CM2
2
CF0_2_CM1
1
CF0_2_CM0
0 TNXTPTR*
to be sent to external command buffers. CFIFO0
is not triggered. CFIFO5 is triggered and sends
(a)
TNXTPTR – Transfer Next Data Pointer.
CFx_ADCa_CMn – Command n in CFIFOx bound for external command buffer a.
*
Command Buffer 3
CF5_3_CM1
1
CF5_3_CM0
0
eQADC SSI
two commands to external command buffer 3.
CFIFO5
CF5_3_CM3
3
CF5_3_CM2
2
Sent
1
Sent
0
TNXTPTR*
Command Buffer 2
CF0_2_CM1
1
CF0_2_CM0
0
CFIFO0 is triggered and sent two commands to external
CFIFO0
CF0_2_CM3
3
CF0_2_CM2
2
Sent
1
Sent
0
TNXTPTR*
command buffer 2. CFIFO5 cannot send commands to
external command buffer 3 because the eQADC SSI is
(b)
Command Buffer 3
CF5_3_CM1
1
Empty
0
eQADC SSI
busy transferring commands from CFIFO0. Execution of
first command of CFIFO5 is completed.
CFIFO5
CF5_3_CM3
3
CF5_3_CM2
2
Sent
1
Sent
0
TNXTPTR*
Command Buffer 2
CF0_2_CM2
1
CF0_2_CM1
0
Execution of first command of CFIFO0 is
CFIFO0
CF0_2_CM3
3
Sent
2
Sent
1
Sent
0
TNXTPTR*
completed and CFIFO0 sends new command
to external command buffer 2.
(c)
Command Buffer 3
CF5_3_CM1
1
Empty
0
eQADC SSI
CFIFO5
CF5_3_CM3
3
CF5_3_CM2
2
Sent
1
Sent
0
TNXTPTR*
Command Buffer 2
CF0_2_CM3
1
CF0_2_CM2
0
Second command in external command buffer 3
CFIFO0
Sent
3
Sent
2
Sent
1
Sent0
TNXTPTR*
completes. Command buffer 3 became empty before
the complete command sequence in CFIFO5 is sent
(d)
Command Buffer 3
Empty
1
Empty
0
to it. NCF5 becomes asserted when the eQADC
receives an indication that command buffer 3 is empty,
by the BUSY fields in the returning serial message.