External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-78 Freescale Semiconductor
— Modified TSIZ[0:1] functionality to only indicate size of current transfer, not give information
on ensuing transfers that be part of the same atomic sequence
— The BL field of the base register has inverted logic from the MPC56x devices (0 = eight-beat
burst on the MPC5xxx, 1 = eight-beat burst on the MPC56x)
• Removed reservation support on external bus
• Removed address type (AT), write-protect (WP), and dual-mapping features because these
functions can be replicated by memory management unit (MMU) in e200z6 core
• Removed support for 8-bit ports
• Removed boot chip select operation: on-chip boot assist module (BAM) handles boot (and
configuration of EBI registers)
• Open drain mode and pullup resistors no longer required for multi-master systems, extra cycle
needed to switch between masters
• Modified arbitration protocol to require extra cycles when switching between masters
• Added support for 32-bit coherent read and write non-chip select accesses in 16-bit data bus mode
• Misaligned accesses are not supported
• Calibration features implemented by four calibration chip selects
• Removed support for three-master systems
• Address decoding for external master accesses uses 4-bit code to determine internal slave instead
of straight address decode
To Next Page