NXP Semiconductors MPC5566 - Page 693

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-14 Freescale Semiconductor
The following table describes the fields in the eMIOS channel control register:
Table 17-9. EMIOS_CCRn Field Description
Field Description
0
FREN
Freeze enable. If set and validated by FRZ bit in EMIOS_MCR, freezes all registers values when in debug
mode, allowing the MCU to perform debug functions.
0 Normal operation
1 Freeze UC registers values
1
ODIS
Output disable. Allows output disable in any output mode except GPIO.
0 The output pin operates normally
1 If the selected output disable input signal is asserted, the output pin goes to the complement of EDPOL
for OPWFM, OPWFMB, and OPWMB modes, but the unified channel continues to operate normally; that
is, it continues to produce FLAG and matches. When the selected output disable input signal is negated,
the output pin operates normally.
2–3
ODISSL[0:1]
Output disable select. Selects one of the four output disable input signals.
00 output disable input 0
01 output disable input 1
10 output disable input 2
11 output disable input 3
4–5
UCPRE[0:1]
Prescaler. Selects the clock divider value for the unified channel internal prescaler, as shown in the following
table:
6
UCPREN
Prescaler enable. Enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value
1 Prescaler enabled
UCPRE[0:1] Divide Ratio
00 1
01 2
10 3
11 4