Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-35
21.4.10 Using the LIN Hardware
The eSCI provides special support for the LIN protocol. It can be used to automate most tasks of a LIN
master. In conjunction with the DMA interface it is possible to transmit entire frames (or sequences of
frames) and receive data from LIN slaves without any CPU intervention. There is no special support for
LIN slave mode. If required, LIN slave mode can be implemented in software.
A LIN frame consists of a break character (10 or 13 bits), a sync field, an ID field, n data fields (n could
be 0) and a checksum field. The data and checksum bytes are either provided by the LIN master (TX frame)
or by the LIN slave (RX frame). The header fields are always generated by the LIN master.
Figure 21-23. Typical LIN frame
The LIN hardware is highly configurable. This configurability allows the eSCI’s LIN hardware to generate
frames for LIN slaves from all revisions of the LIN standard. The settings are adjusted according to the
capabilities of the slave device.
To activate the LIN hardware, the LIN mode bit in the ESCIx_LCR needs to be set. Other settings, such
as double stop flags after bit errors and automatic parity bit generation, are also available for use in LIN
mode.
LIN CKERR Checksum error detected. If an RX frame has the checksum checking
flag set and the last byte does not match the calculated checksum, the
checksum error (CKERR) flag is set. Clear the CKERR flag by writing
a 1 to the bit.
ESCIx_SR[22] CKIE
LIN FRC LIN frame completed. The frame complete (FRC) flag is set after the
last byte of a TX frame is transmitted, or after the last byte of an RX
frame is received. The FRC flag indicates that the next frame can be
set up. Clear the FRC flag by writing a 1 to the bit.
Note: The last byte of an outgoing TX frame or incoming RX frame
indicates that the checksum comparison occurred.
Note: It is possible to set the FRC flag before the DMA controller has
completed transferring the last byte from the eSCI port to
system memory. Do not set the FRC flag if the frame will be
processed. For frames that will be processed, use the DMA
controller interrupt.
ESCIx_SR[23] FCIE
LIN OVFL ESCIx_LRR overflow. The overflow (OVFL) flag is set when a byte is
received in the ESCIx_LRR before the previous byte is read. Since the
system is responsible for reading the register before the next byte
arrives, this condition indicates a problem with CPU load. The OVFL
flag is cleared by writing a 1 to the bit.
ESCIx_SR[31] OFIE
Table 21-21. eSCI Interrupt Flags, Sources, Mask Bits, and Descriptions (continued)
Interrupt
Source
Flag Description Source
Local
Enable
Break Sync ID Data Data CSum
...
To Next Page
Loading...
