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Toshiba GR200 Series - (ii) Check logic and settings for synchronous network; (iii) Check logic and settings for asynchronous network; (iv) Bypassing synchronization check

Toshiba GR200 Series
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6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 812 -
Input
Output
SYNCHK logic in SYNCHK2
SYNC02_SCL_F_ECP
560001 800B02EDE2
PLC signals importation from external conditions
SYNC02_LPS_CL_ECP
560001 800B02EDE6
SYNC02_SPS_CL_ECP
560001 800B02EDE5
SYNCHK_Ry (Function ID: 561001)
SYNC02_RY1_USE_STS
560001 800B02EDED
PLC signals for relay selection relating to SYNCHK2
SYNC02_RY2_USE_STS
560001 800B02EDEE
From SYNCHK_Ry2
&
From SYNCHK_Ry1
SYNCHK2 (Function ID: 560001)
560001 860B021F61
&
Off
On
SYNC02-Split_SYN_EN
SYNC02-SYNCHK2EN
560001 870B021F62
560001 850B021F60
&
&
SYNC02_TSYN2
t 0
0.0 to 100.0s
SYNC02_TSYN
560001 8C0B021F67
SYNC02_SYN_CLC
Sync success
SYNC02_SBP
DPSY01 (Function ID: 511001)
511001 8B02021E48
DPSY02_OEC_RCV
From DPSY02
To DPSY02
SYNC02_SCK_CS09
SYNC02_SCK_CS04
SYNC02_SCK_CS03
SYNC02_SCK_CS02
SyncRy1-Ɵ≈0
SyncRy1-
SyncRy1-dV
SyncRy1-df
SyncRy1-Ɵ less
ΔƟ1 less
ΔƟ1
ΔƟ1≈0
Δf1
ΔV1
&
&
&
&
&
SyncRy2-Ɵ≈0
SyncRy2-
SyncRy2-dV
SyncRy2-df
SyncRy2-Ɵ less
ΔƟ2 less
ΔƟ2
ΔƟ2≈0
Δf2
ΔV2
&
&
&
&
&
&
560001 850B021F59
SYNC02_SYN_CLC
1
t 0
0.0 to 1800.0s
&
560001 880B021F6E
SYNC02_SCK_CS01
560001 890B021F53
SYNC02_LPS_CLC
&
SYNC02_SPS_CLC
5600018 D0B021F51
SYNC02_SCL_F
Sync Failed
Sync bypass
From SYNCHK2
SYNCHK2 (Function ID: 560001)
560001 870B021F77
560001 880B021F78
&
&
SYNC02_Ry_Ang_0Time
SYNC02_Ry_Ang_RDC
560001 820B021F56
560001 850B021F59
560001 800B021F54
SYNC02_SCK_CS16
560001 840B021F5F
Check for synchronous network
Close command (Operate)
Check for asynchronous network
SYNC02_SBP_SSP
560001 800B02EDE1
Bypassing condition
On
SyncRy1-dfEN
SyncRy2-dfEN
On
SYNC02_SBK_CSP
560001 800B02EDEB
&
1
Blocking
Figure 4.6-15 Synchronization check logic in SYNCHK2
(ii) Check logic and settings for synchronous network
As shown in Figure 4.6-14, the V, ∆θ, and f signals are required to check the synchronous
condition; the three signals are input to the logic. The sync-success signal SYNC01_SYN_CLC
is provided after the operation of the delay timer SYNC01_TSYN. The user can regulate the
timer using the setting [SYNC01_TSYN].
(iii) Check logic and settings for asynchronous network
In Figure 4.6-14, the ‘∆θ10 and ‘∆θ1_less signals are used to check the synchronization
condition when the user sets On for scheme switch [SYNC01-Split_SYN_EN]; subsequently
sequentially the sync-success signal SYNC01_SYN_CLC is issued for the DPSY01 function.
(iv) Bypassing synchronization check
If the user wishes to remove the synchronization check, set Off for the scheme switch [SYNC01-
SYNCHK1EN]. The DPSY01 function can operate with the absence of the sync-success signal

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