Toshiba GR200 Series - 4.7.3 Interlock-check method; (i) Node and input;output signals

6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 827 -
Table 4.7-2 Names of operators used in the Interlock-check formulae
Interlock
operator
Sign of
interlock
operator
Description‡
Example of
interlock
formula†
AND(•)
If both input signals are “1”, the resultant
output signal is “1”. If not, the output signal
is “0”.
Q1 • Q2
OR(+)
If either input signals is “1”, the resultant
output signal is “1”. If not, the output signal
is “0”.
Q1 + Q2
NOT(!)
If the input signal is “1”, the resultant output
signal is “0”. If not, the output signal is “1”.
!(Q1)
COMP
Two input signals are compared. If the input
signals are identical, the output signal is “1”.
If not, the output signal is “0”.
(Q1) COMP (1)
†Note: Q1 and Q2 represent controllable objects.
‡Note: For further information, see section 4.7.3(iii).
4.7.3 Interlock-check method
(i) Node and input/output signals
A node is represented by an interlock-operator, input signals (stVal and Quality), and output
signals (stVal and Quality). For example, Figure 4.7-3 shows a node with an “OR” interlock-
operator, input signals, and an output signal. When stVal and ‘Quality’ are applied to the
inputs of the node, the resultant output signal is in accordance with the operation rule of “OR”.
(For details, see 4.7.3(iii)-2)
OR (+)
Node
stVal
Quality
stVal
Input(A)
Input(B)
Output
Quality
stVal
Quality
Figure 4.7-3 Input/output signals
Note: A bold line reflects a signal “stVal”. A thin line reflects a signal “Quality”. The user
should note that the signal format generated by control functions should be
transposed for the stVal format, as shown in Table 4.7-8.