8400 HighLine | Parameter setting & configuration
Device control (DCTRL)
Synchronisation of the internal time base of the controller
90 L Firmware ≤ 05.00 - DMS 4.2 EN - 02/2010
If a value > 0 is set, the start of the application will be delayed by the set time, compared
to the synchronisation signal.
Example: If the phase position is set to 400 μs, the system part of the application starts
400 μs after the arrival of the synchronisation signal.
Sync correction increment
If the cycle times of the synchronisation signal and the phase-locking loop (PLL) are
different, the setting in C01124
defines the correction increments for the phase-locking
loop.
The recommended reset time for the system bus as synchronisation source in case of
occurring deviations is 75 ns (Lenze setting).
efesotomasyon.com - Lenze
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