Lenze E84AVHC Series - 14.1.56 L_DFlipFlop_2

8400 HighLine | Parameter setting & configuration
Function library
Function blocks | L_DFlipFlop_2
946 L Firmware ≤ 05.00 - DMS 4.2 EN - 02/2010
If the bClr input = TRUE:
 Due to the priority bClr > bClk, bD the bOut output signal can be set any time to the
FALSE state by the bClr input signal = TRUE.
 The output signal is kept in this state independent of the other input signals.
14.1.56 L_DFlipFlop_2
The FB saves binary signals (DFlipFlop) in a clock-controlled way.
Inputs
Outputs
Identifier
Data type
Information/possible settings
bD
BOOL
Data input
bClk
BOOL
Clock input
• Only FALSE/TRUE edges are evaluated
bClr
BOOL
Reset input
TRUE • The bOut output is set to FALSE.
•The bNegOut output is set to TRUE.
Identifier
Data type
Value/meaning
bOut
BOOL
Output signal
bNegOut
BOOL
Output signal, inverted
 For a detailed functional description see L_DFlipFlop_1.
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