Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-11
11
BERR
Bit error. Indicates a bit on the bus did not match the transmitted bit. If FBR = 0, checking happens after a complete
byte has been transmitted and received again. If FBR = 1, checking happens bit by bit. This bit is only used for LIN
mode. BERR is also set if an unrequested byte is received (i.e. a byte that is not part of an RX frame) that is not
recognized as a wake-up flag. (Because the data on the RX line does not match the idle state that was assigned to
the TX line.) Clear BERR by writing 1 to it. A bit error causes the LIN finite state machine (FSM) to reset unless
ESCIx_LCR[LDBG] is set.
12–14 Reserved.
15
RAF
Receiver active flag. RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search.
RAF is cleared when the receiver detects an idle character.
0 No reception in progress.
1 Reception in progress.
16
RXRDY
The eSCI has received LIN data. This bit is set when the ESCIx_LCR receives a byte. Write a one to RXRDY to clear
it to 0.
17
TXRDY
The LIN FSM can accept another write to ESCIx_LTR. This bit is set when the ESCIx_LTR register becomes free.
Write a one to TXRDY to clear it to 0.
18
LWAKE
Received LIN wake-up signal. A LIN slave has sent a wake-up signal on the bus. When this signal is detected, the
LIN FSM resets. If the setup of a frame had already started, it therefore must be repeated.
LWAKE is set if ESCI receives a LIN 2.0 wake-up signal (in which the baud rate is lower than 32K baud). Refer to
the WU bit.
19
STO
Slave time out. Represents a NO_RESPONSE_ERROR. This is set if a slave does not complete a frame within the
specified maximum frame length. For LIN 1.3 the following formula is used:
20
PBERR
Physical bus error. No valid message can be generated on the bus. This is set if, after the start of a byte transmission,
the input remains unchanged for 31 cycles. This resets the LIN FSM.
21
CERR
CRC error. The CRC pattern received with an extended frame was not correct.
0 No error
1 CRC error
22
CKERR
Checksum error. Checksum error on a received frame.
23
FRC
Frame complete. LIN frame completely transmitted. All LIN data bytes received.
24–30 Reserved.
31
OVFL
ESCIx_LRR overflow. The LIN receive register has not been read before a new data byte, CRC, or checksum byte
has been received from the LIN bus. Set when the condition is detected, and cleared by writing 1 to it.
Table 21-6. ESCIx_SR Field Descriptions (continued)
Field Description
TFRAME_MAX 10 NDATA 44+×()1.4×=
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