NXP Semiconductors MPC5566 - Page 126

Signal Description
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 2-45
V
DD33
3.3 V
V
FLASH
3.3 V
V
RC33
3.3 V
V
RCCTL
3.3 V
V
RCVSS
3.3 V
V
PP
2
5.0 V
V
DDE
1.8–3.3 V
V
DDEH
3.3–5.0 V
V
STBY
0.8–1.2 V
V
SSA1
GND
V
SSSYN
—
V
SS
GND REF V
SS
NC —
1
These are nominal voltages. V
DDE
is 1.62–3.6 V; V
DDEH
is 3.0–5.5 V. All V
DDE
voltages are ± 10%; V
DDEH
voltages are +5% to –10%. V
RC33
is ± 10%; V
DDSYN
is ± 10%; V
DDA1
voltages are +5% to –10%.
2
During read operations, VPP can be as high as 5.3 V and as low as 3.0 V.
Table 2-3. MPC5566 Device Power/Ground Segmentation for the 496 Pin Assembly
Power
Segment
Voltage
Range
1
I/O Pins Powered by Segment
V
DDA0
5.0 V AN[22:35]
V
DDA1
5.0 V
AN[0]_DAN0+, AN[1]_DAN0-, AN[2]_DAN1+, AN[3]_DAN1-, AN[4]_DAN2+, AN[5]_DAN2-,
AN[6]_DAN3+, AN[7]_DAN3-, AN[8]_ANW, AN[9]_ANX, AN[10]_ANY, AN[11]_ANZ, AN[16:21],
AN[36:39]
V
SSA0
GND V
SSA0
V
SSA1
GND V
SSA1
V
DDE2
1.8–3.3 V
CS
[0], CS[1:3]_ADDR[9:11]_GPIO[1:3], ADDR[8:29]_GPIO[4:25],
ADDR[30:31]_ADDR[6:7]_GPIO[26:27], RD_WR_GPIO[62], BDIP_GPIO[63],
WE
/BE[0:1]_GPIO[64:65], WE/BE[2:3]_GPIO[66:67], TS_GPIO[69], TA_GPIO[70],
TEA
_GPIO[71], TSIZ[0:1]_GPIO[60:61]
V
DDE3
2
1.8–3.3 V
DATA[0:15]_GPIO[28:43], DATA[16]_FEC_TX_CLK_GPIO[44],
DATA[17]_FEC_CRS_GPIO[45], DATA[18]_FEC_TX_ER_GPIO[46],
DATA[19]_FEC_RX_CLK_GPIO[47], DATA[20]_FEC_TXD[0]_GPIO[48],
DATA[21]_FEC_RX_ER_GPIO[49], DATA[22]_FEC_RXD[0]_GPIO[50],
DATA[23]_FEC_TXD[3]_GPIO[51], DATA[24]_FEC_COL_GPIO[52],
DATA[25]_FEC_RX_DV_GPIO[53], DATA[26]_FEC_TX_EN_GPIO[54],
DATA[27]_FEC_TXD[2]_GPIO[55], DATA[28]_FEC_TXD[1]_GPIO[56],
DATA[29]_FEC_RXD[1]_GPIO[57], DATA[30]_FEC_RXD[2]_GPIO[58],
DATA[31]_FEC_RXD[3]_GPIO[59], OE
_GPIO[68], BR_FEC_MDC_GPIO[72],
BG
_FEC_MDIO_GPIO[73], BB_GPIO[74], GPIO[206:207]
Table 2-2. MPC5566 Device Power/Ground Segmentation (continued)
Power Segment
Voltag e
Range
1
I/O Pins Powered by Segment