e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-11
— Interrupt vector prefix register (IVPR) and the interrupt vector offset registers
(IVOR1–IVOR15). These registers together provide the address of the interrupt handler for
different classes of interrupts.
— Save/restore registers (SRR0, SRR1). SRR0 holds the effective address for the instruction at
which execution resumes when an rfi instruction is executed at the end of a non-critical class
interrupt handler routine. SRR1 is used to save machine state on a non-critical interrupt, and
stores the MSR register contents. The MSR value is restored when an rfi instruction is executed
at the end of a non-critical class interrupt handler routine.
— Critical save/restore registers (CSRR0, CSRR1). CSRR0 holds the effective address for the
instruction at which execution resumes when an rfci instruction is executed at the end of a
critical class interrupt handler routine. CSRR1 is used to save machine state on a critical
interrupt, and stores the MSR register contents. The MSR value is restored when an rfci
instruction is executed at the end of a critical class interrupt routine.
• Debug facility registers
— Debug control registers (DBCR0–DBCR2). These registers provide control for enabling and
configuring debug events.
— Debug status register (DBSR). This register contains debug event status.
— Instruction address compare registers (IAC1–IAC4). These registers contain addresses and/or
masks which are used to specify instruction address compare debug events.
— Data address compare registers (DAC1, DAC2). These registers contain addresses and/or
masks which are used to specify data address compare debug events.
— e200z6 does not implement the data value compare registers (DVC1, DVC2).
• Timer registers
— The clock inputs for the timers are connected to the internal system clock.
— Time base (TB). The TB is a 64-bit structure provided for maintaining the time of day and
operating interval timers. The TB consists of two 32-bit registers, time-base upper (TBU) and
time-base lower (TBL). The time-base registers can be written to by supervisor-level software
only, but can be read by both user and supervisor-level software.
— Decrementer register (DEC). This register is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay.
— Decrementer auto-reload (DECAR). This register is provided to support the auto-reload feature
of the decrementer.
— Timer control register (TCR). This register controls decrementer, fixed-interval timer, and
watchdog timer options.
— Timer status register (TSR). This register contains status on timer events and the most recent
watchdog timer-initiated processor reset.
For more details about these registers, refer to the Power Architecture embedded category specifications.
To Next Page
Loading...
