e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-27
4:7
WDD
Way data disable.
0 = The corresponding way is available for replacement by data miss line fills.
1 = The corresponding way is not available for replacement by data miss line
fills.
Bit 4 corresponds to way 0.
Bit 5 corresponds to way 1.
Bit 6 corresponds to way 2.
Bit 7 corresponds to way 3.
The WID and WDD bits can be used for locking ways of the cache, and also are used
in determining the replacement policy of the cache.
8AWID
Additional ways instruction disable.
0 = Additional ways beyond 0–3 are available for replacement by instruction
miss line fills.
1 = Additional ways beyond 0–3 are not available for replacement by instruction
miss line fills.
For the 32KB 8-way cache, ways 4–7 are considered additional ways. When configured
as a 4-way cache, this bit is ignored.
9AWDD
Additional ways data disable.
0 = Additional ways beyond 0–3 are available for replacement by data miss line
fills.
1 = Additional ways beyond 0–3 are not available for replacement by data miss
line fills.
For the 32KB 8-way cache, ways 4–7 are considered additional ways. When configured
as a 4-way cache, this bit is ignored.
10 WAM
Way access mode
0 = Disable way access is checked not enabled for replacement on an access
type are still checked for a cache hit for accesses of that type but are not
replaced by an access miss of that type.
1 = Ways not enabled for replacement on a particular access type (instruction
vs. data) via the AWID, WID, AWDD, and WDD fields are disabled and no
lookup is performed for accesses of that type. Selecting WAM = 1 helps
minimize power consumption.
Software must ensure that the instruction to data coherency is maintained
when using the power-saving feature of the WAM control. Cache must be
invalidated prior to changing the value of this bit. Use of a dcbf followed by
an icbi, msync, isync for modified lines which can be executed is required to
maintain proper operation.
11 CWM
Cache write mode
0 = Cache operates in writethrough mode
1 = Cache operates in copyback mode
When set to writethrough mode, the “W” page attribute from an optional MMU is
ignored and all writes are treated as writethrough required. When set, write
accesses are performed in copyback mode unless the “W” page attribute from
an optional MMU is set.
12 DPB
Disable push buffer
0 = Push buffer enabled
1 = Push buffer disabled
Table 3-9. L1CSR0 Field Descriptions (continued)
Bits Name Description
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