NXP Semiconductors MPC5566 - Page 186

Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 4-17
The following figure shows the reset configuration timing:
Figure 4-4. Reset Configuration Timing
RSTOUT
RESET
Internal
reset
V
DD
POR
PLL
PLL locks
RSTCFG
WKPCFG and BOOTCFG
are latched. PLLCFG and
User drives
config pins relative
to RSTOUT
PLLCFG and RSTCFG are
(4 clock cycles)
PLL locked
2400
1
clock cycles
‘Don’t Care’ and WKPCFG is
treated as ‘1’ during POR
assertion.
PLLCFG, RSTCFG and WKPCFG
are applied, but not latched.
RSTCFG
still applied
1
This clock count is dependent on the configuration of the FMPLL (Refer to Section 4.2.2, “RSTOUT”). If the FMPLL is configured
for 1:1 (dual controller) operation or for bypass mode, this clock count is 16000.
All reset signals
negated (2404 cycles)
PLLCFG is latched.
RSTCFG
is no longer
used.
but not latched.
Crystal powering up or acquiring lock