Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
5-2 Freescale Semiconductor
• Require supervisor privilege level for access
• Restrict access to a trusted master only
• Write-protect the peripheral to deny all access
Refer to Table 5-1 for a list of master/slave IDs and the peripherals for with each master and slave.
Refer to Section 13.3.2.9, “Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR)” for
more information on access protection
Table 5-1. Peripheral Bridge Master/Slave ID Table
XBAR Port XBS port Module Master ID Peripheral
Master 0 e200z6 Core—CPU 0 —
e200z6—Nexus 1 —
Master 1 eDMA 2 —
Master 2 EBI 3 —
Master 3 FEC 4 —
Slave 0 FLASH —
Slave 1 EBI —
Slave 3 SRAM —
Slave 6 PBRIDGE A PBRIDGE A
FMPLL
EBI control
FLASH control
SIU
eMIOS
eTPU reg
eTPU PRAM
eTPU PRAM mirror
eTPU SCM
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