System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-13
Except for a POR request or writing a 1 to the software external reset flag (SERF) bit, all reset requests,
regardless of priority are not serviced until the current reset completes.
5
CRS
Checkstop reset status.
0 The last reset source acknowledged by the reset controller was not an enabled checkstop reset.
1 The last reset source acknowledged by the reset controller was an enabled checkstop reset.
6–13 Reserved
14
SSRS
Software system reset status.
0 The last reset source acknowledged by the reset controller was not a software system reset.
1 The last reset source acknowledged by the reset controller was a software system reset.
15
SERF
Software external reset flag.
0 The software external reset input to the reset controller was not asserted, or this bit has been cleared by writing
a 1 to it.
1 The software external reset input to the reset controller was asserted while this bit was 0.
16
WKPCFG
Weak pull configuration pin status
0 The WKPCFG pin value latched during the last reset was a logical 0 and weak pulldown is the default setting.
1 The WKPCFG pin value latched during the last reset was a logical 1 and weak pullup is the default setting.
17–28 Reserved
29–30
BOOTCFG
Reset configuration pin status.
BOOTCFG[0:1] identifies the address of the reset configuration halfword (RCHW) and whether arbitration is used
by the boot assist module (BAM).
00 Internal boot mode – lowest address (0x0000_0000) from one of the six LAS fields in internal flash memory.
01 Serial boot mode – lower halfword of the censorship control word.
10 External boot mode – lowest address (0x0000_0000) of external memory as defined by the chip select 0
(CS
[0]) signal with no external arbitration.
11 Invalid value – External boot mode with external arbitration.
If RSTCFG
does not assert before RSTOUT negates, and the lower half of the censorship control word (least
significant halfword) equals 0xFFFF or 0x0000, the BOOTCFG field is set to 0b10. Otherwise, if the RSTCFG
pin
was negated at the last negation of RSTOUT,
and the lower half of the censorship control word does not equal
0xFFFF or 0x0000, then the BOOTCFG field is set to the value 0b00.
Refer to Ta ble 4 - 10 for a description of RCHW.
31
RGF
Reset glitch flag.
Set by the reset controller when a glitch is detected on the RESET
pin. This bit is cleared by the assertion of the
power-on reset input to the reset controller, or a write of 1 to the RGF bit. Refer to Section 6.4.2.1, “RESET Pin
Glitch Detect,” for more information on glitch detection.
0 No glitch has been detected on the RESET
pin.
1 A glitch has been detected on the RESET
pin.
Table 6-8. SIU_RSR Field Descriptions
Field Description
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