NXP Semiconductors MPC5566

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Enhanced Direct Memory Access (eDMA)

MPC5566 Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 9-21

channel completion indicators, setting the transfer control descriptor DONE flag and the possible assertion

of an interrupt request, are not affected when an error is detected.

The contents of this register can also be polled and a non-zero value indicates the presence of a channel

error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in

this register and it provides a single bit indication of any errors. The state of any given channel’s error

indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes

to EDMA_ERH or EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status.

A 0 in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CER

is provided so the error indicator for a single channel can easily be cleared.

Address: Base + 0x0028 Access: User R/W

0123456789101112131415

ERR

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ERR

Reset0000000000000000

Figure 9-18. eDMA Error High Register (EDMA_ERH)

Address: Base + 0x002C Access: User R/W

0123456789101112131415

ERR

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ERR

Reset0000000000000000

Figure 9-19. eDMA Error Low Register (EDMA_ERL)

Table 9-15. EDMA_ERH, EDMA_ERL Field Descriptions

Field Description

0–63

ERRn

eDMA Error n.

0 An error in channel n has not occurred.

1 An error in channel n has occurred.

NXP Semiconductors MPC5566 - Page 382