NXP Semiconductors MPC5566 - Page 434

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-21
eSCI
0x0920 146
ESCIA_SR[TDRE]
ESCIA_SR[TC]
ESCIA_SR[RDRF]
ESCIA_SR[IDLE]
ESCIA_SR[OR]
ESCIA_SR[NF]
ESCIA_SR[FE]
ESCIA_SR[PF]
ESCIA_SR[BERR]
ESCIA_SR[RXRDY]
ESCIA_SR[TXRDY]
ESCIA_SR[LWAKE]
ESCIA_SR[STO]
ESCIA_SR[PBERR]
ESCIA_SR[CERR]
ESCIA_SR[CKERR]
ESCIA_SR[FRC]
ESCIA_SR[OVFL]
Combined interrupt requests of eSCI Module A:
• LIN status register 1
• LIN status register 2
• SCI status register 2
• Transmit data register empty
• Transmit complete
• Receive data register full
• Idle line
•Overrun
• Noise flag
• Framing error flag
• Parity error flag interrupt requests
• Bit error interrupt request
• Receive data ready
• Transmit data ready
• Received LIN wakeup signal
• Slave timeout
• Physical bus error
• CRC error
• Checksum error
• Frame complete interrupts requests
• Receive register overflow
0x0930–0x0940 147–148 Reserved
0x0950 149
ESCIB_SR[TDRE]
ESCIB_SR[TC]
ESCIB_SR[RDRF]
ESCIB_SR[IDLE]
ESCIB_SR[OR]
ESCIB_SR[NF]
ESCIB_SR[FE]
ESCIB_SR[PF]
ESCIB_SR[BERR]
ESCIB_SR[RXRDY]
ESCIB_SR[TXRDY]
ESCIB_SR[LWAKE]
ESCIB_SR[STO]
ESCIB_SR[PBERR]
ESCIB_SR[CERR]
ESCIB_SR[CKERR]
ESCIB_SR[FRC]
ESCIB_SR[OVFL]
Combined interrupt requests of eSCI Module B:
• LIN status register 1
• LIN status register 2
• SCI status register 2
• Transmit data register empty
• Transmit complete
• Receive data register full
• Idle line
•Overrun
• Noise flag
• Framing error flag
• Parity error flag interrupt requests
• Bit error interrupt request
• Receive data ready
• Transmit data ready
• Received LIN wakeup signal
• Slave timeout
• Physical bus error
• CRC error
• Checksum error
• Frame complete interrupts requests
• Receive register overflow
0x0960–0x0970 150–151 Reserved
Table 10-9. MPC5566 Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description