Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 11-17
Table 11-5. FMPLL_SYNSR Field Descriptions
Field Description
0–21 Reserved.
22
LOLF
Loss-of-lock flag. Provides the interrupt request flag. This is a write 1 to clear (w1c) bit; to clear the flag, the
user must write a 1 to the bit. Writing 0 has no effect. This flag is not set and an interrupt is not requested, if
the loss-of-lock condition was caused by:
• a system reset
• a write to the FMPLL_SYNCR which modifies the MFD bits
• enabling frequency modulation
If the flag is set due to a system failure, writing the MFD bits or enabling FM does not clear the flag. Asserting
reset clears the flag. This flag bit is sticky; if lock is reacquired, the bit remains set until either a write of 1 or
reset is asserted.
0 Interrupt service not requested
1 Interrupt service requested
Note: Upon a loss-of-lock that is not generated by:
•a system reset
•a write to the FMPLL_SYNCR that modifies the MFD or PREDIV bits
•enabling of frequency modulation
the LOLF is set only if LOLIRQ is set. If the FMPLL reacquires lock and any of the previous conditions
in the bulleted list occurs, the LOLF is set again. To avoid generating an unintentional interrupt, clear
LOLIRQ before changing MFD or PREDIV, or before enabling FM after a previous interrupt and relock
occurred.
23
LOC
Loss-of-clock status. Indicates whether a loss-of-clock condition is present when operating in crystal
reference, external reference, or dual-controller mode, If LOC = 0, the system clocks are operating normally.
If LOC = 1, the system clocks have failed due to a reference failure or a FMPLL failure. If the read of the LOC
bit and the loss-of-clock condition occur simultaneously, the bit does not reflect the current loss of clock
condition. If a loss-of-clock condition occurs which sets this bit and the clocks later return to normal, this bit
is cleared.
A loss of clock condition can only be detected if LOCEN = 1. LOC is always 0 in bypass mode.
0 Clocks are operating normally
1 Clocks are not operating normally.
24
MODE
Clock mode. Determined at reset, this bit indicates which clock mode the system is utilizing. Refer to
Chapter 4, “Reset,” for details on how to configure the system clock mode during reset.
0 PLL bypass mode.
1 PLL clock mode.
25
PLLSEL
PLL mode select. Determined at reset, this bit indicates in which mode the FMPLL operates. This bit is cleared
in dual-controller and bypass mode. Refer to Chapter 4, “Reset,” for details on how to configure the system
clock mode during reset. Refer to Ta bl e 1 1-1 for more information.
0 Dual-controller mode.
1 Crystal reference or external reference mode.
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