Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
11-26 Freescale Semiconductor
The following steps program the clock frequency without frequency modulation:
1. Determine the value for the PREDIV, MFD, and RFD fields in the synthesizer control register
(FMPLL_SYNCR). Remember to include the ΔF
m
if frequency modulation is enabled. The
amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that
can be paired with an RFD factor to provide the desired frequency. The maximum MFD value that
can be used is determined by the ICO range. Refer to the Data Sheet for the maximum frequency
of the ICO.
2. Change the following in FMPLL_SYNCR:
a) Make sure frequency modulation is disabled (FMPLL_SYNCR[DEPTH] = 00). A change to
PREDIV, MFD, or RATE while modulation is enabled invalidates the previous calibration
results.
b) Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU goes into reset when MFD is
written.
c) Initialize the FMPLL for less than the desired final system frequency (done in one single write
to FMPLL_SYNCR):
– Disable LOLIRQ.
– Write FMPLL_SYNCR[PREDIV] to a desired final value.
– Write FMPLL_SYNCR[MFD] to a desired final value.
– Write the RFD control field value to a desired final RFD value plus one.
3. Wait for the FMPLL to lock by monitoring the FMPLL_SYNSR[LOCK] bit. Refer to
Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR),” for memory synchronization
between changing FMPLL_SYNCR[MFD] and monitoring the lock status.
4. Initialize the FMPLL to the desired final system frequency by changing FMPLL_SYNCR[RFD].
The FMPLL does not need to re-lock if only the RFD changes, and the RFD must be set to greater
than one to protect from overshoot.
5. Re-enable LOLIRQ.
NOTE
When using crystal reference mode or external reference mode, do not set
the PREDIV value to any value that causes the phase and frequency detector
to go below 4 MHz. That is, the crystal or external clock frequency divided
by the PREDIV value must be in the range of 4–20 MHz.
NOTE
This first register write causes the FMPLL to switch to an initial system
frequency which is less than the final one. Keeping the change of frequency
to a lower initial value helps minimize the current surge to the external
power supply caused by the change in frequency. The last step changes the
RFD to get the desired final frequency.
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