NXP Semiconductors MPC5566 - Page 585

Flash Memory
MPC5566 Microcontroller Reference Manual, Rev. 2
13-20 Freescale Semiconductor
Table 13-14. FLASH_BIUCR Field Descriptions
Bits Description
0-10 Reserved
11-15 Master n prefetch enable. Used to control whether prefetching can be triggered based on the master ID of a
requesting master. These bits are cleared by hardware reset. Refer to 1.
0 No prefetching can be triggered by this master
1 Prefetching can be triggered by this master
These fields are identified as follows:
M4PFE = FEC
M3PFE= EBI
M2PFE= eDMA
M1PFE= Nexus
M0PFE= MCU core
16–18
APC
1
Address pipelining control. Used to control the number of cycles between pipelined access requests. This
field must be set to a value corresponding to the operating frequency of the system clock. The required
settings are documented in Table 13-15.
000 Reserved
001 Access requests require one hold cycle
010 Access requests require two hold cycles
...
110 Access requests require 6 hold cycles
111 No address pipelining
19–20
WWSC
1
Write wait state control. Used to control the timing for array writes. This field must be set to a value
corresponding to the operating frequency of the system clock. The required settings are documented in
Table 13-15.
00 Reserved
01 One wait state
10 Two wait states
11 Three wait states
21–23
RWSC
1
Read wait state control. Used to control the flash array access time for array reads. This field must be set to
a value corresponding to the operating frequency of the system clock. The required settings are documented
in Table 13-15.
000 Zero wait states
001 One wait state
...
111 Seven wait states
24–25
DPFEN
Data prefetch enable. Enables or disables prefetching initiated by a data read access. This field is cleared by
hardware reset.
00 No prefetching is triggered by a data read access
01 Prefetching can be triggered only by a data burst read access
10 Reserved
11 Prefetching can be triggered by any data read access
26–27
IPFEN
Instruction prefetch enable. Enables or disables prefetching initiated by an instruction read access. This field
is cleared by hardware reset.
00 No prefetching is triggered by an instruction read access
01 Prefetching can be triggered only by an instruction burst read access
10 Reserved
11 Prefetching can be triggered by any instruction read access