Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-55
Registers A1 and B1 define the leading and trailing edges of the PWM output pulse, respectively.
MODE[6] bit controls the transfer from register B2 to B1, which can be done either immediately
(MODE[6] cleared), providing the fastest change in the duty cycle, or at every match of register A1
(MODE[6] set).
The value loaded in register A1 is compared with the value on the selected time base. When a match on
comparator A occurs, the output flip-flop is set to the value of the EDPOL bit. When a match occurs on
comparator B, the output flip-flop is set to the complement of the EDPOL bit.
FLAG can be generated at match B, when MODE[5] is cleared, or in both matches, when MODE[5] is set.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on A or B respectively. The FLAG bit is not set by the FORCMA and FORCMB
operations.
If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,
regardless of the state of the FLAG bit.
To achieve 0% duty cycle, both registers A1 and B1 must be set to the same value. When a simultaneous
match on comparators A and B occur, the output flip-flop is set at every period to the value of EDPOL bit.
0% duty cycle is possible by writing 0x000000 to register A. When a match occurs, the output flip-flop is
set at every period to the complement of EDPOL bit. The transfer from register B2 to B1 is still controlled
by MODE[6] bit.
NOTE
If A1 and B1 are set to the 0x000000, a 100% duty cycle waveform is
produced.
NOTE
Updates to the A register always occur immediately. If next period update is
selected via the mode[6] bit, only the B register update is delayed until the
next period.
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