Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-9
— A host service request allows activation of a channel thread by the device core request.
— Each channel has an event mechanism that supports single and double action functionality in
various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal or equal-only comparator.
• Two independent 24-bit time bases for channel synchronization
— The first time base can be clocked by the system clock with programmable prescaler division
from 2 to 512 (in steps of 2).
— The first time base can also be clocked by an external signal with programmable prescaler
divisions of 1 to 256.
— The second time base can be clocked by an external signal with programmable prescaler
divisions from 1 to 64 or by the system clock divided by 8.
— The second time base has a programmable prescaler that applies to all TCR2 clock inputs
except the angle counter.
— The second time base counter can work as an angle counter, enabling angle-based applications
to match angle instead of time.
— The second time base can alternatively be used as a pulse accumulator gated by an external
signal.
— Either time base can be written or read by either eTPU engine at any time.
— Either time base can be read, but not written, by the host.
— Both time bases can be exported or imported from engine to engine through the STAC (shared
time and counter) bus.
NOTE
An engine cannot export or import to or from itself. An engine cannot
import a time base and/or angle count if it is in angle mode.
• Event-triggered RISC processor (microengine)
— 2-stage pipeline implementation (fetch and execution), with separate instruction memory
(SCM) and data memory (SDM).
— Two-system-clock microcycle fixed-length instruction execution for the ALU.
— 20 KB of shared code memory (SCM).
— Interleaved SCM access in dual-engine eTPU (MPC5566) avoids contention in time for
instruction memory.
— 4 KB of shared data memory (SDM)
— Interleaved SDM access in dual-engine eTPU (MPC5566) avoids contention in time for
instruction memory.
— Instruction set with embedded channel support, including specialized channel control
subinstructions and conditional branching on channel-specific flags.
— Channel-oriented addressing: channel-bound address mode with host configured channel base
address allows the same function to operate independently on different channels.
— Channel-bound data address space of up to 128 32-bit parameters (512 bytes).
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