NXP Semiconductors MPC5566 - Page 801

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-44 Freescale Semiconductor
NOTE
The device core must write 1 to clear a status bit.
NOTE
In this device, eTPU A channels [0:2,12:15,28:29] and eTPU B channels
[0:3,12:15,28:31] are connected to the DMA. The data transfer request lines
that are not connected to the DMA controller are left disconnected and do
not generate transfer requests, even if their request status bits assert in
registers ETPU_CDTRSR and ETPU_CnSCR
Address: Channel_Register_Base + 0x0004 Access: R/W
012345678 9 101112131415
RCISCIOS000000DTRSDTROS000000
W w1c w1c w1c w1c
Reset000000000 0 000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RIPSOPS0000000 0 0000
FM
W
Reset000000000 0 000000
Figure 18-23. eTPU Channel n Status Control Register (ETPU_CnSCR)
Table 18-26. ETPU_CnSCR Field Descriptions
Field Description
0
CIS
Channel interrupt status.
0 Channel has no pending interrupt to the device core.
1 Channel has a pending interrupt to the device core.
CIS is mirrored in the ETPU_CISR. For more information on ETPU_CISR and interrupts, refer to Section 18.4.5.1,
“eTPU Channel Interrupt Status Register (ETPU_CISR),” and the eTPU Reference Manual.
The core must write 1 to clear CIS.
1
CIOS
Channel interrupt overflow status.
0 Interrupt overflow negated for this channel
1 Interrupt overflow asserted for this channel
CIOS is mirrored in the ETPU_CIOSR. For more information on the ETPU_CIOSR and interrupt overflow, refer to
Section 18.4.5.3, “eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)” and the eTPU Reference
Manual.
The core must write 1 to clear CIOS.
2–7 Reserved
8
DTRS
Data transfer request status.
0 Channel has no pending data transfer request.
1 Channel has a pending data transfer request.
DTRS is mirrored in the ETPU_CDTRSR. For more information on the ETPU_CDTRSR and data transfer, refer to
Section 18.4.5.2, “eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)” and the eTPU
Reference Manual.
The core must write 1 to clear DTRS.