Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-24 Freescale Semiconductor
4
CFUFn
CFIFO underflow flag n. Indicates an underflow event on CFIFOn. CFUFn is set when CFIFOn is in the TRIGGERED
state and it becomes empty. No commands are transferred from an underflowing CFIFO, and command transfers
from lower priority CFIFOs are not blocked. When CFUIEn (see Section Section 19.3.2.7, “eQADC Interrupt and
eDMA Control Registers 0–5 (EQADC_IDCRn)”) and CFUFn are both asserted, the eQADC generates an interrupt
request.
Apart from generating an independent interrupt request for a CFIFOn underflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are enabled). Refer to Section 19.4.7, “eQADC
eDMA/Interrupt Request,” for details. Writing a 1 clears CFUFn. Writing a 0 has no effect.
0 No CFIFO underflow event occurred
1 A CFIFO underflow event occurred
5
SSSn
CFIFO single-scan status bit n. When asserted, enables the detection of trigger events for CFIFOs programmed into
single-scan level- or edge-trigger mode, and works as trigger for CFIFOs programmed into single-scan
software-trigger mode. Refer to Section 19.4.3.5.2, “Single-Scan Mode,” for further details. The SSSn bit is set by
writing a 1 to the SSEn bit (see Section Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5
(EQADC_CFCRn)”). The eQADC clears the SSSn bit when a command with an asserted EOQ bit is transferred from
a CFIFO in single-scan mode, when a CFIFO is in single-scan level trigger mode and its status changes from the
TRIGGERED state due to the detection of a closed gate, or when the value of the CFIFO operation mode MODEn
(see Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn)”) is changed to disabled. Writing to
SSSn has no effect. SSSn has no effect in continuous-scan or in disabled mode.
0 CFIFO in single-scan, level-, or edge-trigger mode ignores trigger events, or CFIFO in single-scan software-trigger
mode is not triggered.
1 CFIFO in single-scan level- or edge-trigger mode detects a trigger event, or CFIFO in single-scan software-trigger
mode is triggered.
6
CFFFn
CFIFO fill flag n. CFFFn is set when the CFIFOn is not full. When CFFEn (see Section 19.3.2.7, “eQADC Interrupt
and eDMA Control Registers 0–5 (EQADC_IDCRn)”) and CFFFn are both asserted, an interrupt or an eDMA request
is generated depending on the status of the CFFSn bit. When CFFSn is negated (interrupt requests selected),
software clears CFFFn by writing a 1 to it. Writing a 0 has no effect. When CFFSn is asserted (eDMA requests
selected), CFFFn is automatically cleared by the eQADC when the CFIFO becomes full.
0 CFIFOn is full.
1 CFIFOn is not full.
Note: When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be cleared in the ISR after
the CFIFOn push register is accessed.
Note: CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected).
7–11 Reserved.
Table 19-12. EQADC_FISRn Field Descriptions (continued)
Field Description
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