Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-60 Freescale Semiconductor
CFFE is asserted as in Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn),” the eQADC generates requests for more commands from a command queue. An
interrupt request, served by the host CPU, is generated when CFFS is negated, and a eDMA request, served
by the eDMA, is generated when CFFS is asserted. The host CPU or the eDMA respond to these requests
by writing to the Section 19.3.2.4, “eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn),” to fill the
CFIFO.
NOTE
Only whole words must be written to EQADC_CFPR. Writing halfwords or
bytes to EQADC_CFPR pushes the entire 32-bit CF_PUSH field into the
corresponding CFIFO, but undefined data fills the areas of CF_PUSH that
were not specifically designated as target locations for writing.
Figure 19-35 describes the important components in the CFIFO. Each CFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The push next data pointer
points to the next available CFIFO location for storing data written into the eQADC command FIFO push
register. The transfer next data pointer points to the next entry to be removed from CFIFOn when it
completes a transfer. The CFIFO transfer counter control logic counts the number of entries in the CFIFO
and generates eDMA or interrupt requests to fill the CFIFO. TNXTPTR in Section 19.3.2.8, “eQADC
FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” indicates the index of the entry that is
currently being addressed by the transfer next data pointer, and CFCTR, in the same register, provides the
number of entries stored in the CFIFO.
Using TNXTPTR and CFCTR, the absolute addresses for the entries indicated by the transfer next data
pointer and by the push next data pointer can be calculated using the following formulas:
Transfer Next Data Pointer Address = CFIFOn_BASE_ADDRESS + TNXTPTRn x 4
Push Next Data Pointer Address = CFIFOn_BASE_ADDRESS +
[(TNXTPTRn+CFCTRn) mod CFIFO_DEPTH] x 4
where
• a mod b returns the remainder of the division of a by b.
• CFIFOn_BASE_ADDRESS is the smallest memory mapped address allocated to a CFIFOn entry.
• CFIFO_DEPTH is the number of entries contained in a CFIFO - four in this implementation.
When CFSn in Section 19.3.2.11, “eQADC CFIFO Status Register (EQADC_CFSR),” is in the
TRIGGERED state, the eQADC generates the proper control signals for the transfer of the entry pointed
by transfer next data pointer. CFUFn in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers
0–5 (EQADC_FISRn),” is set when a CFIFOn underflow event occurs. A CFIFO underflow occurs when
the CFIFO is in the TRIGGERED state and it becomes empty. No commands are transferred from an
underflowing CFIFO, and command transfers from lower priority CFIFOs are not blocked. CFIFOn is
empty when the transfer next data pointer n equals the push next data pointer n and CFCTRn is 0. CFIFOn
is full when the transfer next data pointer n equals the push next data pointer n and CFCTRn is not 0.
When the eQADC completes the transfer of an entry from CFIFOn: the transferred entry is popped from
CFIFOn, the CFIFO counter CFCTR in the Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers
0–5 (EQADC_FISRn),” is decremented by 1, and transfer next data pointer n is incremented by 1 (or
wrapped around) to point to the next entry in the CFIFO. The transfer of entries bound for the on-chip
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