NXP Semiconductors MPC5566 - Page 891

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-88 Freescale Semiconductor
Table 19-47. ADC Clock Configuration Example (System Clock Frequency = 120 MHz)
ADC0/1_CLK_PS[0:4]
System Clock
Divide Factor
ADC Clock in MHz
(System Clock =
120MHz)
Differential Conversion
Speed with Default
Sampling Time
(13 + 2 cycles) in
ksamp/s
Single-Ended
Conversion Speed with
Default Sampling Time
(14 + 2 cycles) in
ksamp/s
0b00000 2 N/A N/A N/A
0b00001 4 N/A N/A N/A
0b00010 6 N/A N/A N/A
0b00011 8 N/A N/A N/A
0b00100 10 12.0 800 750
0b00101 12 10.0 667 625
0b00110 14 8.57 571 536
0b00111 16 7.5 500 469
0b01000 18 6.67 444 417
0b01001 20 6.0 400 375
0b01010 22 5.45 364 341
0b01011 24 5.0 333 313
0b01100 26 4.62 308 288
0b01101 28 4.29 286 268
0b01110 30 4.0 267 250
0b01111 32 3.75 250 234
0b10000 34 3.53 235 221
0b10001 36 3.33 222 208
0b10010 38 3.16 211 197
0b10011 40 3.0 200 188
0b10100 42 2.86 190 179
0b10101 44 2.73 182 170
0b10110 46 2.61 174 163
0b10111 48 2.5 167 156
0b11000 50 2.4 160 150
0b11001 52 2.31 154 144
0b11010 54 2.22 148 139
0b11011 56 2.14 143 134
0b11100 58 2.07 138 129
0b11101 60 2.0 133 125