Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-93
Figure 19-51. On-Chip ADC Control Scheme
MUX
40:1
CFIFOn
ADC0
BIAS
GEN
MUX
40:1
ADC1
MUX
Control
Logic
(32-bits)
RFIFOn
(16-bits)
AN0-AN39
REFBYPC
MA0, MA1,
Configuration
Registers
EMUX0 EMUX1
Entry1
LST0
Entry0
ADC0 Buffer
Entry1
LST1
Entry0
ADC1 Buffer
Register Data 0/1
CHANNEL_NUMBER0
CHANNEL_NUMBER1
MESSAGE_TAG1; FMT1, CAL1
MESSAGE_TAG0;
FMT0, CAL0
Result Format
and
Calibration
Submodule
FIFO
Control
Unit
Result0
Result1
Time Stamp1
Time Stamp0
Time
Stamp
Logic
TBC_CLK_PS
TSR0
TSR1
ADC1_Result1
ADC0_Result0
ADDR or/and DATAADDR or/and DATA
MA2
Configuration Register Fields NOTE: n = 0, 1, 2, 3, 4, 5
REF
GEN
Pre
Charge
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