MPC5566 Reference Manual Addendum, Rev. 2
Revision history
Freescale Semiconductor8
2 Revision history
Table 2 provides a revision history for this document.
Section 6.3.1.125 “Pad
Configuration Register 218
(SIU_PCR218)”
• Changed PA field from two bits to one bit
• Figure 6-126: Change note 2 to “... set the PA field to 0b0”.
• Table 6-122. PCR218 “PA Field Definition” change as shown below:
0b0 FCK
0b1 AN[15]
Section 19.4.5.4.1
“Calibration Overview”
Remove the braces from the equation “CAL_RES = GCC x (RAW_RES + OCC + 2)”.
Section 11.3.1.1
“Synthesizer Control Register
(FMPLL_SYNCR)”
Deleted the last note in PREDIV field description that states:
“To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation
by tying PLLCFG[2] low (set PREDIV to 0b000).”
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Raised Priority Preserved Events
Event Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at
priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector
for that peripheral interrupt request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent
data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing
data block, is the last instruction the processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
H Interrupt exception handler epilog writes to INTC_EOIR.
I LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop
from LIFO is the priority from before peripheral interrupt request 100 interrupted.
ISR108 now can access data block coherently after interrupt exception handler
executes rfi instruction.
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