Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-13
When the DSPI is configured as a SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI is
configured as a SPI bus slave, the DSPIx_CTAR0 register is used.
When the DSPI is configured as a DSI master, the DSICTAS field in the DSPI DSI configuration register
(DSPIx_DSICR) selects which of the DSPIx_CTAR register is used. See Section 20.3.2.10, “DSPI DSI
Configuration Register (DSPIx_DSICR).” When the DSPI is configured as a DSI bus slave, the
DSPIx_CTAR1 register is used.
In CSI configuration, the transfer attributes are selected based on whether the current frame is SPI data or
DSI data. SPI transfers in CSI configuration follow the protocol described for SPI configuration, and DSI
transfers in CSI configuration follow the protocol described for DSI configuration. CSI configuration is
only valid in conjunction with master mode. See Section 20.4.5, “Combined Serial Interface (CSI)
Configuration” for more details.
.
Address:
Base + 0x000C (DSPIx_CTAR0)
Base + 0x0010 (DSPIx_CTAR1)
Base + 0x0014 (DSPIx_CTAR2)
Base + 0x0018 (DSPIx_CTAR3)
Base + 0x001C (DSPIx_CTAR4)
Base + 0x0020 (DSPIx_CTAR5)
Base + 0x0024 (DSPIx_CTAR6)
Base + 0x0028 (DSPIx_CTAR7)
Access: R/W
0123456789101112131415
R
DBR FMSZ CPOL CPHA
LSB
FE
PCSSCK PASC PDT PBR
W
Reset0111100000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset0000000000000000
Figure 20-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
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