Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-20 Freescale Semiconductor
The following table describes the fields in the DSPI status register:
Table 20-6. DSPIx_SR Field Descriptions
Field Description
0
TCF
Transfer complete flag. Indicates that all bits in a frame have been shifted out. The TCF bit is set after the
last incoming databit is sampled, but before the tASC delay starts. See Section 20.4.7.1, “Classic SPI
Transfer Format (CPHA = 0)” for details. The TCF bit is cleared by writing 1 to it.
0 Transfer not complete
1Transfer complete
1
TXRXS
TX and RX status. Reflects the status of the DSPI. See Section 20.4.2, “Start and Stop of DSPI Transfers”
for information on what clears and sets this bit.
0 TX and RX operations are disabled (DSPI is in STOPPED state)
1 TX and RX operations are enabled (DSPI is in RUNNING state)
2 Reserved
3
EOQF
End of queue flag. Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set
when the TX FIFO entry has the EOQ bit set in the command halfword and after the last incoming databit
is sampled, but before the tASC delay starts. See Section 20.4.7.1, “Classic SPI Transfer Format (CPHA =
0)” for details.
The EOQF bit is cleared by writing 1 to it. When the EOQF bit is set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI command
Note: EOQF does not function in slave mode.
4
TFUF
Transmit FIFO underflow flag. Indicates that an underflow condition in the TX FIFO has occurred. The
transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty, and
a transfer is initiated by an external SPI master. The TFUF bit is cleared by writing 1 to it.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
5 Reserved
6
TFFF
Transmit FIFO fill flag. Indicates that the TX FIFO can be filled. Provides a method for the DSPI to request
more entries to be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can
be cleared by writing 1 to it, or an by acknowledgement from the eDMA controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
7–11 Reserved
12
RFOF
Receive FIFO overflow flag. Indicates that an overflow condition in the RX FIFO has occurred. The bit is set
when the RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
13 Reserved
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