NXP Semiconductors MPC5566 - Page 1057

MPC5566 Microcontroller Reference Manual, Rev. 2
22-20 Freescale Semiconductor
See Section 22.4.7, “Interrupts,” for more details.
NOTE
A read clears BIT1ERR, BIT0ERR, ACKERR, CRCERR, FRMERR, and
STFERR, therefore these bits must not be read speculatively. For future
compatibility, the TLB entry covering the CANx_ESR must be configured
to be guarded.
Address: Base + 0x0020 Access: User R/W
0123456789101112131415
R
0 0 0 0 0 000000000
TWRN
INT
RWRN
INT
W w1c w1c
Reset00000000000000 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RBIT1
ERR
BIT0
ERR
ACK
ERR
CRC
ERR
FRM
ERR
STF
ERR
TX
WRN
RX
WRN
IDLE TXRX FLTCONF 0
BOFF
INT
ERR
INT
0
W
w1c w1c
Reset00000000000000 0 0
Figure 22-9. Error and Status Register (CANx_ESR)
Table 22-12. CANx_ESR Field Descriptions
Field Description
0–13 Reserved.
14
TWRNINT
If the WRNEN bit in CANx_MCR is asserted, the TWRNINT bit is set when the TXWRN flag transitions
from 0 to 1, meaning that the TX error counter reached 96. If the corresponding mask bit in the
Control Register (TWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing to 1. Writing 0 has no effect.
0 No such occurrence
1 TXECTR ≥ 96
15
RWRNINT
If the WRNEN bit in CANx_MCR is asserted, the RWRNINT bit is set when the RXWRN flag transitions
from 0 to 1, meaning that the RX error counter reached 96. If the corresponding mask bit in the
Control Register (RWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing to 1. Writing 0 has no effect.
0 No such occurrence
1RXECTR ≥ 96
16
BIT1ERR
Bit 1 error. Indicates when an inconsistency occurs between the transmitted and the received message in
a bit. A read clears BIT1ERR.
0 No such occurrence
1 At least one bit sent as recessive is received as dominant
Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending
a passive error flag that detects dominant bits.
17
BIT0ERR
Bit 0 error. Indicates when an inconsistency occurs between the transmitted and the received message in
a bit. A read clears BIT0ERR.
0 No such occurrence
1 At least one bit sent as dominant is received as recessive