MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-21
18
ACKERR
Acknowledge error. Indicates that an acknowledge error has been detected by the transmitter node; that
is, a dominant bit has not been detected during the ACK SLOT. A read clears ACKERR.
0 No such occurrence
1 An ACK error occurred since last read of this register
19
CRCERR
Cyclic redundancy code error. Indicates that a CRC error has been detected by the receiver node; that is,
the calculated CRC is different from the received. A read clears CRCERR.
0 No such occurrence
1 A CRC error occurred since last read of this register.
20
FRMERR
Form error. Indicates that a form error has been detected by the receiver node; that is, a fixed-form bit field
contains at least one illegal bit. A read clears FRMERR.
0 No such occurrence
1 A form error occurred since last read of this register
21
STFERR
Stuffing error. Indicates that a stuffing error has been detected. A read clears STFERR.
0 No such occurrence.
1 A stuffing error occurred since last read of this register.
22
TXWRN
TX error counter. This status bit indicates that repetitive errors are occurring during message transmission.
0 No such occurrence
1 TXECTR ≥ 96
23
RXWRN
RX error counter. This status bit indicates when repetitive errors are occurring during messages reception.
0 No such occurrence
1RXECTR ≥ 96
24
IDLE
CAN bus IDLE state. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence
1CAN bus is now IDLE
25
TXRX
Current FlexCAN2 status (transmitting/receiving). This status bit indicates if FlexCAN2 is transmitting or
receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is
asserted.
0 FlexCAN2 is receiving a message (IDLE = 0)
1 FlexCAN2 is transmitting a message (IDLE = 0)
26–27
FLTCONF[0:1]
Fault confinement state. This status bit indicates the confinement state of the FlexCAN2 module. If the
LOM bit in the CANx_CR asserts, the FLTCONF field indicates “Error Passive”. Since the CANx_CR is not
affected by a soft reset, the FLTCONF field is not affected by a soft reset if the LOM bit asserts.
00 Error active
01 Error passive
1X Bus off
28 Reserved.
29
BOFFINT
Bus off interrupt. This status bit is set when FlexCAN2 is in the bus off state. If CANx_CR[BOFFMSK] is
set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 FlexCAN2 module is in ‘Bus Off’ state
Table 22-12. CANx_ESR Field Descriptions (continued)
Field Description
To Next Page
Loading...
