Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5-11
PBRIDGE_A_OPACR2 PBRIDGE_A_Base + 0x0048 0 eTPU 0b0100
1 — 0b0100
2 eTPU PRAM 0b0100
3 eTPU PRAM mirror 0b0100
4 eTPU SCM 0b0100
5–7 — 0b0100
PBRIDGE B
PBRIDGE_B_PACR0 PBRIDGE_B_Base + 0x0020 0 PBRIDGE B 0b0101
1 XBAR 0b0100
2–7 — 0b0000
PBRIDGE_B_PACR2 PBRIDGE_B_Base + 0x0028 0 ESCM 0b0100
1 eDMA 0b0100
2 INTC 0b0100
3 — 0b0100
4–7 — 0b0000
PBRIDGE_B_OPACR0 PBRIDGE_B_Base + 0x0040 0 eQADC 0b0100
1–3 — 0b0100
4 DSPI A 0b0100
5 DSPI B 0b0100
6 DSPI C 0b0100
7 DSPI D 0b0100
PBRIDGE_B_OPACR1 PBRIDGE_B_Base + 0x0044 0–3 — 0b0100
4 eSCI A 0b0100
5 eSCI B 0b0100
6-7 — 0b0100
PBRIDGE_B_OPACR2 PBRIDGE_B_Base + 0x0048 0 FlexCAN A 0b0100
1 FlexCAN B 0b0100
2 FlexCAN C 0b0100
3 FlexCAN D 0b0100
4–7 — 0b0100
PBRIDGE_B_OPACR3 PBRIDGE_B_Base + 0x004C 0 — 0b0100
1–6 — 0b0100
7 BAM 0b0100
Table 5-6. PACR and OPACR Access Control Registers and Peripheral Mapping (continued)
Register Register Address
Peripheral
Access Field #
Peripheral Type
Access Field
Default Value
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