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NXP Semiconductors MPC5566 - Page 367

NXP Semiconductors MPC5566
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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-6 Freescale Semiconductor
Base + 0x0126 EDMA_CPR38 eDMA channel 38 priority register 8
Base + 0x0127 EDMA_CPR39 eDMA channel 39 priority register 8
Base + 0x0128 EDMA_CPR40 eDMA channel 40 priority register 8
Base + 0x0129 EDMA_CPR41 eDMA channel 41 priority register 8
Base + 0x012A EDMA_CPR42 eDMA channel 42 priority register 8
Base + 0x012B EDMA_CPR43 eDMA channel 43 priority register 8
Base + 0x012C EDMA_CPR44 eDMA channel 44 priority register 8
Base + 0x012D EDMA_CPR45 eDMA channel 45 priority register 8
Base + 0x012E EDMA_CPR46 eDMA channel 46 priority register 8
Base + 0x012F EDMA_CPR47 eDMA channel 47 priority register 8
Base + 0x0130 EDMA_CPR48 eDMA channel 48 priority register 8
Base + 0x0131 EDMA_CPR49 eDMA channel 49 priority register 8
Base + 0x0132 EDMA_CPR50 eDMA channel 50 priority register 8
Base + 0x0133 EDMA_CPR51 eDMA channel 51 priority register 8
Base + 0x0134 EDMA_CPR52 eDMA channel 52 priority register 8
Base + 0x0135 EDMA_CPR53 eDMA channel 53 priority register 8
Base + 0x0136 EDMA_CPR54 eDMA channel 54 priority register 8
Base + 0x0137 EDMA_CPR55 eDMA channel 55 priority register 8
Base + 0x0138 EDMA_CPR56 eDMA channel 56 priority register 8
Base + 0x0139 EDMA_CPR57 eDMA channel 57 priority register 8
Base + 0x013A EDMA_CPR58 eDMA channel 58 priority register 8
Base + 0x013B EDMA_CPR59 eDMA channel 59 priority register 8
Base + 0x013C EDMA_CPR60 eDMA channel 60 priority register 8
Base + 0x013D EDMA_CPR61 eDMA channel 61 priority register 8
Base + 0x013E EDMA_CPR62 eDMA channel 62 priority register 8
Base + 0x013F EDMA_CPR63 eDMA channel 63 priority register 8
Base + 0x0140–0x0FFF — Reserved —
Base + 0x1000 TCD00 eDMA transfer control descriptor 00 256
Base + 0x1020 TCD01 eDMA transfer control descriptor 01 256
Base + 0x1040 TCD02 eDMA transfer control descriptor 02 256
Base + 0x1060 TCD03 eDMA transfer control descriptor 03 256
Base + 0x1080 TCD04 eDMA transfer control descriptor 04 256
Base + 0x10A0 TCD05 eDMA transfer control descriptor 05 256
Table 9-1. eDMA 32-bit Memory Map (continued)
Address Register Name Register Description Bits

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