NXP Semiconductors MPC5566 - Page 404

Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-43
eQADC_FISR3_RFDF3 7 EQADC.FISR3[RFDF3] eQADC Receive FIFO 3 Drain Flag
eQADC_FISR4_CFFF4 8 EQADC.FISR4[CFFF4] eQADC Command FIFO 4 Fill Flag
eQADC_FISR4_RFDF4 9 EQADC.FISR4[RFDF4] eQADC Receive FIFO 4 Drain Flag
eQADC_FISR5_CFFF5 10 EQADC.FISR5[CFFF5] eQADC Command FIFO 5 Fill Flag
eQADC_FISR5_RFDF5 11 EQADC.FISR5[RFDF5] eQADC Receive FIFO 5 Drain Flag
DSPIB_SR_TFFF 12 DSPIB.SR[TFFF] DSPIB Transmit FIFO Fill Flag
DSPIB_SR_RFDF 13 DSPIB.SR[RFDF] DSPIB Receive FIFO Drain Flag
DSPIC_SR_TFFF 14 DSPIC.SR[TFFF] DSPIC Transmit FIFO Fill Flag
DSPIC_SR_RFDF 15 DSPIC.SR[RFDF] DSPIC Receive FIFO Drain Flag
DSPID_SR_TFFF 16 DSPID.SR[TFFF] DSPID Transmit FIFO Fill Flag
DSPID_SR_RFDF 17 DSPID.SR[RFDF] DSPID Receive FIFO Drain Flag
eSCIA_COMBTX 18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
eSCIA combined DMA request of the Transmit Data
Register Empty, Transmit Complete, and LIN Transmit
Data Ready DMA requests
eSCIA_COMBRX 19 ESCIA.SR[RDRF] ||
ESCIA.SR[RXRDY]
eSCIA combined DMA request of the Receive Data
Register Full and LIN Receive Data Ready DMA
requests
eMIOS_GFR_F0 20 EMIOS.GFR[F0] eMIOS channel 0 Flag
eMIOS_GFR_F1 21 EMIOS.GFR[F1] eMIOS channel 1 Flag
eMIOS_GFR_F2 22 EMIOS.GFR[F2] eMIOS channel 2 Flag
eMIOS_GFR_F3 23 EMIOS.GFR[F3] eMIOS channel 3 Flag
eMIOS_GFR_F4 24 EMIOS.GFR[F4] eMIOS channel 4 Flag
eMIOS_GFR_F8 25 EMIOS.GFR[F8] eMIOS channel 8 Flag
eMIOS_GFR_F9 26 EMIOS.GFR[F9] eMIOS channel 9 Flag
eTPU_CDTRSR_A_DTRS0 27 ETPU.CDTRSR_A[DTRS0] eTPUA Channel 0 Data Transfer Request Status
eTPU_CDTRSR_A_DTRS1 28 ETPU.CDTRSR_A[DTRS1] eTPUA Channel 1 Data Transfer Request Status
eTPU_CDTRSR_A_DTRS2 29 ETPU.CDTRSR_A[DTRS2] eTPUA Channel 2 Data Transfer Request Status
eTPU_CDTRSR_A_DTRS14 30 ETPU.CDTRSR_A[DTRS14] eTPUA Channel 14 Data Transfer Request Status
eTPU_CDTRSR_A_DTRS15 31 ETPU.CDTRSR_A[DTRS15] eTPUA Channel 15 Data Transfer Request Status
DSPIA_SR_TFFF 32 DSPIAISR[TFFF] DSPIA Transmit FIFO Fill Flag
DSPIA_SR_RFDF 33 DSPIA.SR[RFDF] DSPIA Receive FIFO Drain Flag
eSCIB_COMBTX 34 ESCIB.SR[TDRE] ||
ESCIB.SR[TC] ||
ESCIB.SR[TXRDY]
eSCIB combined DMA request of the Transmit Data
Register Empty, Transmit Complete, and LIN Transmit
Data Ready DMA requests
Table 9-23. DMA Request Summary for eDMA (continued)
DMA Request Channel Source Description