NXP Semiconductors MPC5566 - Page 430

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-17
0x0300 48 SIU_EISR[EIF2] SIU external interrupt flag 2
0x0310 49 SIU_EISR[EIF3] SIU external interrupt flag 3
0x0320 50 SIU_EISR[EIF15:EIF4] SIU external interrupt flags 15–4
eMIOS
0x0330 51 EMIOS_GFR[F0] eMIOS channel 0 flag
0x0340 52 EMIOS_GFR[F1] eMIOS channel 1 flag
0x0350 53 EMIOS_GFR[F2] eMIOS channel 2 flag
0x0360 54 EMIOS_GFR[F3] eMIOS channel 3 flag
0x0370 55 EMIOS_GFR[F4] eMIOS channel 4 flag
0x0380 56 EMIOS_GFR[F5] eMIOS channel 5 flag
0x0390 57 EMIOS_GFR[F6] eMIOS channel 6 flag
0x03A0 58 EMIOS_GFR[F7] eMIOS channel 7 flag
0x03B0 59 EMIOS_GFR[F8] eMIOS channel 8 flag
0x03C0 60 EMIOS_GFR[F9] eMIOS channel 9 flag
0x03D0 61 EMIOS_GFR[F10] eMIOS channel 10 flag
0x03E0 62 EMIOS_GFR[F11] eMIOS channel 11 flag
0x03F0 63 EMIOS_GFR[F12] eMIOS channel 12 flag
0x0400 64 EMIOS_GFR[F13] eMIOS channel 13 flag
0x0410 65 EMIOS_GFR[F14] eMIOS channel 14 flag
0x0420 66 EMIOS_GFR[F15] eMIOS channel 15 flag
eTPU A
0x0430 67 ETPU_MCR[MGEA]
ETPU_MCR[MGEB]
ETPU_MCR[ILFA]
ETPU_MCR[ILFB]
ETPU_MCR[SCMMISF]
eTPU global exception
0x0440 68 ETPU_CISR_A[CIS0] eTPU engine A channel 0 interrupt status
0x0450 69 ETPU_CISR_A[CIS1] eTPU engine A channel 1 interrupt status
0x0460 70 ETPU_CISR_A[CIS2] eTPU engine A channel 2 interrupt status
0x0470 71 ETPU_CISR_A[CIS3] eTPU engine A channel 3 interrupt status
0x0480 72 ETPU_CISR_A[CIS4] eTPU engine A channel 4 interrupt status
0x0490 73 ETPU_CISR_A[CIS5] eTPU engine A channel 5 interrupt status
0x04A0 74 ETPU_CISR_A[CIS6] eTPU engine A channel 6 interrupt status
Table 10-9. MPC5566 Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description