Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-18 Freescale Semiconductor
0x04B0 75 ETPU_CISR_A[CIS7] eTPU engine A channel 7 interrupt status
0x04C0 76 ETPU_CISR_A[CIS8] eTPU engine A channel 8 interrupt status
0x04D0 77 ETPU_CISR_A[CIS9] eTPU engine A channel 9 interrupt status
0x04E0 78 ETPU_CISR_A[CIS10] eTPU engine A channel 10 interrupt status
0x04F0 79 ETPU_CISR_A[CIS11] eTPU engine A channel 11 interrupt status
0x0500 80 ETPU_CISR_A[CIS12] eTPU engine A channel 12 interrupt status
0x0510 81 ETPU_CISR_A[CIS13] eTPU engine A channel 13 interrupt status
0x0520 82 ETPU_CISR_A[CIS14] eTPU engine A channel 14 interrupt status
0x0530 83 ETPU_CISR_A[CIS15] eTPU engine A channel 15 interrupt status
0x0540 84 ETPU_CISR_A[CIS16] eTPU engine A channel 16 interrupt status
0x0550 85 ETPU_CISR_A[CIS17] eTPU engine A channel 17 interrupt status
0x0560 86 ETPU_CISR_A[CIS18] eTPU engine A channel 18 interrupt status
0x0570 87 ETPU_CISR_A[CIS19] eTPU engine A channel 19 interrupt status
0x0580 88 ETPU_CISR_A[CIS20] eTPU engine A channel 20 interrupt status
0x0590 89 ETPU_CISR_A[CIS21] eTPU engine A channel 21 interrupt status
0x05A0 90 ETPU_CISR_A[CIS22] eTPU engine A channel 22 interrupt status
0x05B0 91 ETPU_CISR_A[CIS23] eTPU engine A channel 23 interrupt status
0x05C0 92 ETPU_CISR_A[CIS24] eTPU engine A channel 24 interrupt status
0x05D0 93 ETPU_CISR_A[CIS25] eTPU engine A channel 25 interrupt status
0x05E0 94 ETPU_CISR_A[CIS26] eTPU engine A channel 26 interrupt status
0x05F0 95 ETPU_CISR_A[CIS27] eTPU engine A channel 27 interrupt status
0x0600 96 ETPU_CISR_A[CIS28] eTPU engine A channel 28 interrupt status
0x0610 97 ETPU_CISR_A[CIS29] eTPU engine A channel 29 interrupt status
0x0620 98 ETPU_CISR_A[CIS30] eTPU engine A channel 30 interrupt status
0x0630 99 ETPU_CISR_A[CIS31] eTPU engine A channel 31 interrupt status
eQADC
0x0640 100
EQADC_FISRx[TORF]
EQADC_FISRx[RFOF]
EQADC_FISRx[CFUF]
eQADC combined overrun interrupt request s from
all of the FIFOs:
• Trigger Overrun
• Receive FIFO Overflow
• Command FIFO Underflow
0x0650 101 EQADC_FISR0[NCF] eQADC command FIFO 0 non-coherency flag
0x0660 102 EQADC_FISR0[PF] eQADC command FIFO 0 pause flag
Table 10-9. MPC5566 Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description
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