External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-31
Figure 12-12. Single-Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States
00
DATA is valid
The EBI drives address and control signals an extra cycle because it
version of the external TA
(1 cycle delayed) to terminate
*
*
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
(input)
RD_WR
TSIZ[0:1]
BDIP
OE
CS[n]
uses a latched
the cycle.
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