NXP Semiconductors MPC5566 - Page 536

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-49
Figure 12-31 shows the device connections on the DATA[0:31] bus.
Figure 12-31. Interface to Different Port Size Devices
Table 12-20 lists the bytes required on the data bus for read cycles. The bytes indicated as ‘—’ are not
required during that read cycle.
Table 12-20. Data Bus Requirements for Read Cycles
Transfer
Size
TSIZ[0:1]
Address 32-Bit Port Size 16-Bit Port Size
1
1
Also applies when DBM = 1 for 16-bit data bus mode.
A[30] A[31] D[0:7] D[8:15] D[16:23] D[24:31] D[0:7] D[8:15]
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0 or OP2
2
2
This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3.
OP1 or OP3
031
DATA[16:23]
32-bit port size
DATA[24:31]DATA[8:15]DATA[0:7]
Interface output
register
16-bit port size
OP0 OP1 OP2 OP3
OP0 OP1 OP2 OP3
OP0 OP1
OP2 OP3