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NXP Semiconductors MPC5566 - Page 629

NXP Semiconductors MPC5566
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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-20 Freescale Semiconductor
Table 15-13 describes the fields and functions in the receive control register (RCR):
Table 15-13. RCR Descriptions
Bits Name Description
0–4 Reserved, must be cleared.
5–15
MAX_FL MAX_FL
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and
includes the CRC at the end of the frame. Transmit frames longer than MAX_FL cause
the BABT interrupt to occur. Receive frames longer than MAX_FL cause a BABR
interrupt and sets the LG bit in the end-of-frame receive buffer descriptor. You can
program the default value to 1518 or 1522 (if VLAN tags are supported).
16–25 Reserved, must be cleared.
26
FCE FCE
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame
detection, the transmitter stops transmitting data frames for a given duration.
27
BC_REJ BC_REJ
Broadcast frame reject. If asserted, frames with DA (destination address) =
FF_FF_FF_FF_FF_FF is rejected unless the PROM bit is set. If both BC_REJ and
PROM = 1, then frames with broadcast DA is accepted and the M (MISS) bit is set in the
receive buffer descriptor.
28
PROM PROM
Promiscuous mode. All frames are accepted regardless of address matching.
29
MII_MODE MII_MODE
Media independent interface mode. Selects external interface mode. Setting this bit to
one selects MII mode, setting this bit equal to zero selects 7-wire mode (used only for
serial 10 Mbps). This bit controls the interface mode for both transmit and receive blocks.
30
DRT DRT
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor
transmit activity in half duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
31
LOOP LOOP
Internal loopback. If set, transmitted frames are looped back internal to the device and
the transmit output signals are not asserted. The system clock is substituted for the
FEC_TX_CLK when LOOP is asserted. DRT must be set to zero when asserting LOOP.

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