NXP Semiconductors MPC5566 - Page 719

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-40 Freescale Semiconductor
internal counter is disabled and its content is transferred to register A2. At the same time the FLAG bit is
set. Reading registers EMIOS_ALTAn or A2 returns the amount of detected pulses.
For continuous operation (MODE[6] cleared), the next match between comparator A and the selected time
base clears the internal counter and counting is enabled again. To guarantee the accuracy when reading
EMIOS_CCNTRn after the flag is set, the software must check if the time base value is out of the time
interval defined by registers A1 and B1. Alternatively register A2 always holds the latest available
measurement providing coherent data at any time after the first FLAG occurs. This register is addressed
by the alternate address EMIOS_ALTAn.
For single shot operation (MODE[6] set), the next match between comparator A and the selected time base
has no effect, until a new write to register A is performed. The EMIOS_CCNTRn content is also
transferred to register A2 when a match in the B comparator occurs.
NOTE
The FORCMA and FORCMB bits have no effect when the unified channel
is configured for PEC mode.
Figure 17-27 and Figure 17-28 show how the unified channel can be used for continuous or single shot
pulse/edge counting mode.
Figure 17-27. Pulse/Edge Counting Continuous Mode Example
Selected
counter bus
0x000090 0x000090
B1 value
2
0x000090
0x000303 0x0003030x000303
Amount of
EMIOS_CCNTRn
FLAG
set event
MODE[6] = 0
A1 match B1 match B1 match
A1 value
1
Notes:
1
Writing EMIOS_CADRn writes to A1.
2
Writing EMIOS_CBDRn writes to B1.
Time
0x000000
events
detected
A1 match
A1 and B1
Write
0x000090 0x000303 0x000090 0x000303
A2 value
3
3
Reading EMIOS_ALTAn returns the value of A2.
A2 EMIOS_CCNTRn
A2 EMIOS_CCNTRn