Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-47
17.4.4.4.12 Output Pulse-Width and Frequency Modulation Mode (OPWFM)
The following table lists the output pulse-width and frequency modulation mode settings:
In this mode, the duty cycle is (register A1 + 1) and the period is (register B1 + 1). The MODE[6] bit
controls the transfer from register B2 to B1, which can be done either immediately (MODE[6] cleared),
providing the fastest change in the duty cycle, or at every match of register A1 (MODE[6] set).
The internal counter is automatically selected as a time base, therefore the BSL[0:1] bits in register
EMIOS_CCRn have no meaning. The output flip-flop’s active state is the complement of EDPOL bit. The
output flip-flop is active during the duty cycle (from the start of the cycle until a match occurs in
comparator A). After the match in comparator A the output flip-flop is in the inactive state (the value of
EDPOL) until the next cycle starts. When a match on comparator A occurs, the output flip-flop is set to
the value of the EDPOL bit. When a match occurs on comparator B, the output flip-flop is set to the
complement of the EDPOL bit and the internal counter is cleared.
FLAG can be generated at match B, when MODE[5] is cleared, or in both matches, when MODE[5] is set.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on A or B respectively. Also, FORCMB clears the internal counter. The FLAG
bit is not set by the FORCMA or FORCMB operations.
If subsequent comparisons occur on comparators A and B, the PWFM pulses continue to be output,
regardless of the state of the FLAG bit.
To achieve 0% duty cycle, both registers A1 and B1 must be set to the same value. When a simultaneous
match occurs on comparators A and B, the output flip-flop is set at every period to the value of EDPOL bit.
To temporarily change from the current duty cycle to 0% and then return to the current duty cycle, the
sequence is the following:
1. If not currently stored, store value of register A.
2. Set A=B.
3. If immediate 0% duty cycle is desired, set FORCA=1.
4. To return to the previous duty cycle, restore register A with its former value.
Table 17-24. OPWFM Operating Mode
MODE[0:6] Unified Channel OPWFM Operating Mode
0b0011000 Output pulse-width and frequency modulation. FLAG set at match of internal counter and
comparator B, immediate update.
0b0011001 Output pulse-width and frequency modulation. FLAG set at match of internal counter and
comparator B, next period update.
0b0011010 Output pulse-width and frequency modulation. FLAG set at match of internal counter and
comparator A or comparator B, immediate update.
0b0011011 Output pulse-width and frequency modulation. FLAG set at match of internal counter and
comparator A or comparator B, next period update.
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