Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-48 Freescale Semiconductor
100% duty cycle is possible by writing 0x000000 to register A. When a match occurs, the output flip-flop
is set at every period to the complement of EDPOL bit. The transfer from register B2 to B1 is still
controlled by MODE[6] bit.
To temporarily change from the current duty cycle to 100% and then return to the current duty cycle, the
sequence is the following:
1. If not currently stored, store value of register A.
2. Set A=0.
3. If immediate 100% duty cycle is desired, set FORCB=1.
4. To return to the previous duty cycle, restore register A with its former value.
NOTE
Updates to the A register always occur immediately. If next period update is
selected via the mode[6] bit, only the B register update is delayed until the
next period.
Figure 17-34 shows the unified channel running in OPFWM mode with immediate register update.
Figure 17-34. OPWFM with Immediate Update
A1 value
1
B1 value
B2 value
2
0x001000
0x000900
Output
flip-flop
A1 match A1 match
Time
0x000000
B1 match
0x000200
0x001000
0x000900
0x000200
Write to
A2 and B2
0x000200 0x000200
Write to
B2
0x000900
EMIOS_CCNTRn
MODE[6] = 0
B1 match
0x001000
0x001000
0x000900
Notes:
1
Writing EMIOS_An writes to A2.
2
Writing EMIOS_Bn writes to B2.
A2 value transferred to A1 according to OUn bit.
B2 value transferred to B1 according to OUn bit.
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