Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-52 Freescale Semiconductor
At any time, the FORCMA or FORCMB bits are equivalent to a successful comparison on comparator A
or B with the exception that the FLAG bit is not set.
NOTE
When in freeze mode, the FORCMA or FORCMB bits only allow the
software to force the output flip-flop to the level corresponding of a match
on A or B respectively.
If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,
regardless of the state of the FLAG bit.
To achieve a duty cycle of 100%, both registers A1 and B1 must be set to the same value. When a
simultaneous match occurs between the selected time base and registers A1 and B1, the output flip-flop is
set at every period to the value of EDPOL bit and the selected time base switches to the selected counter
bus, allowing a new cycle to begin at any time, as previously described. 0% duty cycle is possible by
writing 0x000000 to register A. When a match occurs, the output flip-flop is set at every period to the
complement of EDPOL bit and the selected time base switches to the selected counter bus, allowing a new
cycle to begin at any time, as previously described. In both cases, FLAG is generated regardless of
MODE[5] bit.
NOTE
If A1 and B1 are set to the 0x000000, a 0% duty cycle waveform is
produced.
NOTE
Any updates to the A or B register takes place immediately.
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