NXP Semiconductors MPC5566 - Page 741

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-62 Freescale Semiconductor
Figure 17-45 shows the generated output signal if A1 is 0. Since the counter does not reach zero in this
mode, the channel internal logic infers a match as if A1 = 1, with the difference that in this case the positive
edge of the match signal is used to trigger the output flip-flop transition instead of the positive edge that is
used when A1 = 1. The A1 positive edge match signal from cycle (n+1) occurs at the same time as the B1
match negative edge from cycle (n). This allows the use of the A1 match positive edge to mask the B1
match negative edge when they occur at the same time. The result is that no transition occurs on the output
flip-flop, and a 0% duty cycle is generated.
Figure 17-45. eMIOS OPWFMB Mode Example — A1 = 0 (0% Duty Cycle)
1
4
5
A1 value
0x000004
A1 match
A1 match negative
Output flip-flop
EMIOS_CCNTRn
Time
B1 Match negative edge detect
B1 match
B1 match negative
B1 value 0x000008
System clock
Prescaled clock
A2 value 0x000000
0x000000
A1 match positive
A1 Match positive edge detect
No transition at this point
1
Cycle n
Cycle n+1
edge Detection
edge detection
edge detection
A1 match
negative
edge detect
EDPOL = 0
Write to A2