Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-70 Freescale Semiconductor
Figure 17-52 shows a 100% duty cycle output signal generated by setting A1 = 4 and B1 = 3. In this case
the trailing edge is positioned at the boundary of cycle (n+1), which is actually considered to belong to
cycle (n+2) and therefore does not cause the output flip-flip to transition.
Figure 17-52. eMIOS PWMCB Mode Example — 100% Duty Cycle (A1 = 4, B1 = 3)
The output disable input, if enabled, causes the output flip-flop to transition to the compliment of EDPOL.
This allows to the channel output flip-flop to be forced to a safety state. The internal channel matches
continue to occur in this case, thus generating flags. When the output disable is negated, the channel output
flip-flop is again controlled by A1 and B1 matches. This process is synchronous, meaning that the output
channel pin transitions only occur on system clock edges.
Like in OPWMB and OPWFMB modes, the match signal used to set or clear the channel output flip-flop
is generated on the negation of the channel comparator output signal which compares the selected time
base with A1 or B1. Refer to Figure 17-44, which illustrates the delay from matches to output flip-flop
transition in OPWFMB mode.
0x000001
0x000020
0x000004
A1 value
A2 value
B1 value
B2 value
0x000004
0x000001
Output flip-flop
0x000003
0x000015
0x000003
0x000015
0x000003
Selected
counter bus
Time
Write to B2
Time
Cycle n Cycle n+1 Cycle n+2
Dead-time
Dead-time
Dead-time
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