NXP Semiconductors MPC5566 - Page 823

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-20 Freescale Semiconductor
Table 19-11. EQADC_IDCRn Field Descriptions
Field Description
0
NCIEn
Non-coherency interrupt enable n. Enables the eQADC to generate an interrupt request when the corresponding
NCFn, described in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” is
asserted.
0 Disable non-coherency interrupt request
1 Enable non-coherency interrupt request
1
TORIEn
Trigger overrun interrupt enable n. Enables the eQADC to generate an interrupt request when the corresponding
TORFn (described in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)”) is
asserted.
Apart from generating an independent interrupt request for a CFIFOn trigger overrun event, the eQADC also
provides a combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt,
and the command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and
TORIEn are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are enabled). Refer to Section 19.4.7, “eQADC
eDMA/Interrupt Request
,” for details.
0 Disable trigger overrun interrupt request
1 Enable trigger overrun interrupt request
2
PIEn
Pause interrupt enable n. Enables the eQADC to generate an interrupt request when the corresponding PFx in
EQADC_FISRn is asserted. Refer to Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn).”
0 Disable pause interrupt request
1 Enable pause interrupt request
3
EOQIEn
End-of-queue interrupt enable n. Enables the eQADC to generate an interrupt request when the corresponding
EOQFn in EQADC_FISRn is asserted. Refer to Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn).”
0 Disable end of queue interrupt request.
1 Enable end of queue interrupt request.
4
CFUIEn
CFIFO underflow interrupt enable n. Enables the eQADC to generate an interrupt request when the corresponding
CFUFn in EQADC_FISRn is asserted.
Apart from generating an independent interrupt request for a CFIFOn underflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are enabled). Refer to Section 19.4.7, “eQADC
eDMA/Interrupt Request,” for details.
0 Disable underflow interrupt request
1 Enable underflow interrupt request
5 Reserved.
6
CFFEn
CFIFO fill enable n. Enables the eQADC to generate an interrupt request (CFFSn is asserted) or eDMA request
(CFFSn is negated) when CFFFn in EQADC_FISRn is asserted. Refer to Section 19.3.2.8, “eQADC FIFO and
Interrupt Status Registers 0–5 (EQADC_FISRn).”
0 Disable CFIFO fill eDMA or interrupt request
1 Enable CFIFO fill eDMA or interrupt request
Note: CFFEn must not be negated while an eDMA transaction is in progress.
7
CFFSn
CFIFO fill select n. Selects if an eDMA or interrupt request is generated when CFFFn in EQADC_FISRn (Refer to
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)”
) is asserted. If CFFEn is
asserted, the eQADC generates an interrupt request when CFFSn is negated, or it generates an eDMA request if
CFFSn is asserted.
0 Generate interrupt request to move data from the system memory to CFIFOn.
1 Generate eDMA request to move data from the system memory to CFIFOn.
Note: CFFSn must not be negated while an eDMA transaction is in progress.