Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-105
Figure 19-58. Slave Driving the msb and Consecutive Bits in a Data Transmission
FCK
SDS
Slave Sample
Input
t
DT
Master’s SDI
2625 1 2 3 ...
End
Transmission
Begin
Transmission
SDS is asserted after positive edge of FCK.
Slave drives second bit due to detection of an
asserted SDS on the negative edge of FCK.
1)
FCK
SDS
Slave Sample
Input
t
DT
Master’s SDI
2625 1 2 3 ...
End
Transmission
Begin
Transmission
SDS is asserted before positive edge of FCK.
Slave drives second bit due to detection of an
asserted SDS on the negative edge of FCK.
2)
FCK
SDS
Slave Sample
Input
t
DT
Master’s SDI
2625 1 2 3 ...
End
Transmission
Begin
Transmission
Slave drives msb bit again due to
detection of a negated SDS
on the
3)
1
negative edge of FCK.
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