Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-120 Freescale Semiconductor
Figure 19-70 is an overview of the eQADC system.
Figure 19-70. eQADC System Overview
The eQADC system consists of four parts: queues in system memory, the eQADC, on-chip ADCs, and an
external device. As compared with the QADC, the eQADC system requires two pieces of extra hardware.
1. An eDMA or an MCU is required to move data between the eQADC’s FIFOs and queues in the
system memory.
2. A serial interface [eQADC synchronous serial interface (SSI)] is implemented to transmit and
receive data between the eQADC and the external device.
Because there are only FIFOs inside the eQADC, much of the terminology or use of the register names,
register contents, and signals of the eQADC involve FIFO instead of queue. These register names, register
contents, and signals are functionally equivalent to the queue counterparts in the QADC. Table 19-59 lists
how the eQADC register, register contents, and signals are related to QADC.
External
triggers
Serial
connection
System bus
DMA/ Interrupt
requests
Trigger and
FIFO control
logic
Analog-to-digital converters (2x)
Command queues Result queuesDMAC/CPU
eQADC SSI
CFIFOs RFIFOs
Analog-to-digital converter
eQADC
External Device
Hardware in eQADC that
was not present in QADC
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